-- INVERTER
entity INVERTER is
  port (
    IN_A: in bit;
    OUT_A: out bit
  );
end INVERTER;
 
architecture BEHAVIOR of INVERTER is
begin
  OUT_A <= not IN_A;
end BEHAVIOR;


-- AOI
entity AOI is
  port (
    IN_A, IN_B, IN_C, IN_D: in bit;
    OUT_A: out bit    
  );
end AOI;

architecture BEHAVIOR of AOI is
  component INVERTER is
    port (
      IN_A: in bit;
      OUT_A: out bit
    );
  end component;
  signal INT_A, INT_B, INT_C: bit;
begin
  INVERTER_A: INVERTER port map (INT_C, OUT_A);
  INT_C <= INT_A or INT_B;
  INT_B <= IN_C and IN_D;
  INT_A <= IN_A and IN_B;
end BEHAVIOR;


-- MUX2
entity MUX2 is
  port (
      IN_A, IN_B, IN_C, IN_D: in bit;
      OUT_A: out bit
  );
end MUX2;

architecture BEHAVIOR of MUX2 is
  component AOI is
    port (
      IN_A, IN_B, IN_C, IN_D: in bit;
      OUT_A: out bit    
    );
  end component;
  component INVERTER is
    port (
      IN_A: in bit;
      OUT_A: out bit
    );
  end component;
  signal INT_A: bit;
begin
  AOI_A: AOI port map (IN_A, IN_B, INT_A, IN_C, OUT_A);
  INVERTER_A: INVERTER port map (IN_A, INT_A);
end BEHAVIOR;


-- TESTBENCH
library ieee;
use ieee.std_logic_1164.all;
entity TESTBENCH is
end TESTBENCH;

architecture BEHAVIOR of TESTBENCH is
  signal TEST_IN_A, TEST_IN_B, TEST_IN_C, TEST_IN_D: bit;
  signal TEST_OUT_A: bit;
begin
  -- Instantiate the unit under test
  uut: entity work.MUX2(BEHAVIOR)
  port map(TEST_IN_A, TEST_IN_B, TEST_IN_C, TEST_IN_D, TEST_OUT_A);
  -- Generate test values
  process (TEST_IN_A, TEST_IN_B, TEST_IN_C, TEST_IN_D)
  begin
    TEST_IN_A <= not TEST_IN_A after  200 ns;
    TEST_IN_B <= not TEST_IN_B after  400 ns;
    TEST_IN_C <= not TEST_IN_C after  800 ns;
    TEST_IN_D <= not TEST_IN_D after 1600 ns;
    -- Break simulation
    assert false
      report "Break"
    severity failure;
  end process;
end BEHAVIOR;